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motorola m68040 users manual b-1 rev2.2 (11/02/99) appendix b MC68EC040 note rev. 2.2 contains timing information for 40 mhz operation. refer to chang bars. some tbd values will be filled in shortly. all references to MC68EC040 also apply to the MC68EC040v. refer to appendix c mc68040v and MC68EC040v for more information on the MC68EC040v. the MC68EC040 is motorola's third generation of m68000-compatible, high-performance, 32-bit microprocessors. the MC68EC040 is an embedded controller employing a highly integrated architecture to provide very high performance in a monolithic hcmos device. the MC68EC040 integrates an mc68040-compatible integer unit, an access control unit (acu), and independent 4-kbyte instruction and data caches. a six-stage instruction pipeline, mul- tiple internal buses, and a full internal harvard architecture, including separate caches for both instruction and data accesses, provides a high degree of instruction execution parallel- ism. the inclusion of on-chip bus snooping logic, which directly supports cache coherency in multimaster applications, enhances cache functionality. the MC68EC040 is user-object-code compatible with previous members of the m68000 family and is speci?cally optimized to reduce the execution time of compiler-generated code. the MC68EC040 is pin compatible with the mc68040 and mc68lc040. the MC68EC040 is implemented in motorola's latest hcmos technology, providing an ideal balance between speed, power, and physical device size. figure b-1 provides a simpli?ed block diagram of the MC68EC040. the main features of the MC68EC040 include: ? mc68040-compatible integer execution unit ? 4-kbyte instruction cache and 4-kbyte data cache accessible simultaneously ? 32-bit, nonmultiplexed external address and data buses with synchronous bursting interface ? user-object-code compatible with all m68000 microprocessors ? concurrent integer unit, acu, and bus controller operation maximizes throughput ? low-latency bus accesses for reduced cache-miss penalty ? multimaster/multiprocessor support via bus snooping ? 4-gbyte direct addressing range
b-2 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) with the exception of the memory management unit (mmu), the ?oating-point unit (fpu), and their respective registers, the MC68EC040 programming model, data formats and types, instruction set (except all instructions beginning with an f, ptest, and pflush), and caches are the same as described in section 1 introduction for the mc68040. figures b-2 and b-3 illustrate the programming model and functional signal groups for the MC68EC040. b.1 MC68EC040 differences the following differences exist between the MC68EC040 and mc68040: ? two independent access control units (acus) replace the mc68040 mmus. the acu has four corresponding registers (access control registers) that the mc68040 imple- ments as data transparent translation registers. the page size is fixed at 4 kbytes. ? ptest and pflush instructions cause an indeterminate result (i.e., an undetermined number of bus cycles); the user should not execute them on the MC68EC040. ? the MC68EC040 does not contain an fpu which causes unimplemented floating-point exceptions to occur using a new stack frame format. figure b-1. MC68EC040 block diagram
motorola m68040 users manual b-3 MC68EC040 rev2.2 (11/02/99) ? the dle and mdis pin names have been changed to js0 and js1, respectively. ? the MC68EC040 does not implement the dle mode, multiplexed, or output buffer im- pedance selection modes of operation. the MC68EC040 implements only the small output buffer mode of operation. all timing and drive capabilities of the MC68EC040 are equivalent to those of the mc68040 in the small buffer mode of operation. b.2 jtag scan (js1Cjs0) the mc68040 mdis and dle pin names have been changed to js1 and js0 respectively. during normal operation, the js1 and js0 pin cannot ?oat, they must be tied to gnd or vcc directly or through a resistor. during board testing, these pins retain the functionality of the jtag scan of the mc68040 for compatibility purposes. refer to section 6 ieee 1149.1a test access port (jtag) for details concerning ieee 1149.1 standard test access port and boundary scan architecture . b.3 access control units the information in this section replaces the information in section 3 memory management unit (except MC68EC040 and MC68EC040v) . when reading section 4 instruction and data caches , disregard any references to the mmu; remember the functionality of the access control registers has replaced that of transparent translation registers. the figure b-2. MC68EC040 programming model
b-4 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) MC68EC040 contains two independent acus, one for instructions and one for data. each acu allows memory selections to be made requiring attributes particular to peripherals, shared memory, or other special memory requirements. the following paragraphs describe the acus and the access control registers contained in them. b.3.1 access control registers each acu has two independent access control registers (acrs). the instruction acu con- tains the instruction access control registers (iacr0 and iacr1). the data acu contains the data access control registers (dacr0 and dacr1). both acrs provide and control sta- tus information for access control of memory in the MC68EC040. only programs that exe- cute in the supervisor mode using the movec instruction can directly access the acrs. the 32-bit acrs each de?ne blocks of MC68EC040:address space for access control. these blocks of address space can overlap or be separate, and are a minimum of 16 mbytes. three blocks are used with two user-de?ned attributes, cachability control and optional write protection. the acrs specify a block of address space as serialized noncach- able for peripheral selections and as write-through for shared blocks of address space in multi-processing applications. the acrs can be con?gured to support many embedded figure b-3. MC68EC040 functional signal groups
motorola m68040 users manual b-5 MC68EC040 rev2.2 (11/02/99) control applications while maintaining cache integrity. refer to section 4 instruction and data caches for details concerning cachability. figure b-4 illustrates the acr format. figure b-4. MC68EC040 access control register format address base this 8-bit field is compared with physical address bits a31Ca24. addresses that match in this comparison (and are otherwise eligible) are accessible. address mask this 8-bit field contains a mask for the address base field. setting a bit in the ad- dress mask field causes the processor to ignore the corresponding bit in the ad- dress base field. setting some of the address mask bits to ones obtains blocks of memory larger than 16 mbytes. the low-order bits of this field are normally set to define contiguous blocks larger than 16 mbytes, although contiguous blocks are not required. eenable this bit enables and disables transparent translation of the block defined by this register. refer to section 3 memory management unit (except MC68EC040 and MC68EC040v) for details on transparent translation. 0 = access control disabled. 1 = access control enabled. ssupervisor/user mode this field specifies the way fc2 is used in matching an address: 00 =match only if fc2 = 0 (user mode access). 01 =match only if fc2 = 1 (supervisor mode access). 10, 11 =ignore fc2 when matching. u1, u0user page attributes these two bits drive on the user page attribute signals (upa1 and upa0). if an external bus transfer results from the access, u0 and u1 are echoed to the upa0 and upa1 signals, respectively. the user can program these bits to support extended addressing, bus snooping, or other applications. the MC68EC040 does not interpret these bits. 31 2423 16151413121110 9876543210 logical address base logical address mask e s 0 0 0 u1 u0 0 cm 0 0 w 0 0
b-6 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) cmcache mode this field selects the cache mode and access serialization for a page as follows: 00 = cachable, write-through 01 = cachable, copyback 10 = noncachable, serialized 11 = noncachable detailed information on caching modes is available in section 4 instruction and data caches , and information on serialization is available in section 7 bus operation . wwrite protect this bit indicates if the transparent block is write protected. if set, write and read-modi- fy-write accesses are aborted as if the r-bit in a table descriptor were clear. refer to 3.2.2 descriptors for a description of table descriptors. 0 = read and write accesses permitted. 1 = write accesses not permitted. b.3.2 address comparison the following description of address comparison assumes that the acrs are enabled. clearing the e-bit in each acr independently disables access control, causing the proces- sor to ignore it. when an acu receives a physical address, the privilege mode and the eight high-order bits of the address are compared to the block of addresses de?ned by the two acrs for the cor- responding acu. each block of address space for an acr contains an s-?eld, a base address ?eld, and an address mask ?eld. the s-?eld allows for matching either user or supervisor accesses (or both). setting a bit in the address mask ?eld causes the cor- responding bit of the address base to be ignored in the address comparison and privi- lege mode. setting successively higher order bits in the address mask ?eld increases the size of the block of address space. the address for the current bus cycle and an acr address match when the privilege mode and address bits for each (not including the masked bits) are equal. each acr speci?es write protection for the block of address space. enabling write protection for a block of address space causes the abortion of write or read-modify-write accesses to the block, and an access error exception occurs. by appropriately con?guring an acr, ?exible mappings can be speci?ed. for example, to control access to the user address space, the s-?eld equals $0, and the address mask ?eld equals $ff in all four acrs. to control access to the supervisor address space ($00000000C$0fffffff) with write protection, the base address ?eld = $0x, the address mask ?eld equals $0f, the w-bit is set to one, and the s-?eld = $1. the inclusion of independent acrs in both the instruction acu (iacu) and data acu (dacu provides an exception to the merged instruction and data address space, allowing different access con- trol for instruction and operand accesses. also, since the instruction memory unit is only used for instruction prefetches, different instruction and data acrs can cause pc relative operand fetches to be translated differently from instruction prefetches.
motorola m68040 users manual b-7 MC68EC040 rev2.2 (11/02/99) matching either of the acrs in a corresponding acu during an access to a memory unit completes the access with the acu. if both registers match, the access uses the xacr0 sta- tus bits. addresses are passed through without translation if there is no match in the acrs and no table search occurs. the MC68EC040 does not perform table searches. b.3.3 effect of rsti on the acu when the assertion of the reset input (rsti ) signal resets the MC68EC040, the e-bits of the acrs are cleared, disabling address access control. b.4 special modes of operation this part of the m68040 user's manual does not apply to the MC68EC040. the MC68EC040 does not sample the ipl2 Cipl0 , cdis , js0 (dle on the mc68040), or js1 (mdis on the mc68040) pins on the rising edge of rsti . an external device asserts rsti to reset the processor. when power is applied to the sys- tem, external circuitry should assert rsti for a minimum of 10 bclk cycles after v cc is within tolerance. figure b-5 is a functional timing diagram of the power-on reset operation, illustrating the relationships between v cc , rsti , and bus signals. the bclk and pclk clock signals are required to be stable by the time v cc reaches the minimum operating spec- i?cation. rsti is internally synchronized for two bclks before being used, and must meet the speci?ed setup and hold times to bclk (speci?cations #51 and #52 in MC68EC040 electrical characteristics ) only if recognition by a speci?c bclk rising edge is required. once rsti is negated, the processor is internally held in reset for another 128 clock cycles. during the reset period, all three-statable signals are three-stated, and the rest are driven to their inactive state. once the internal reset signal negates, all bus signals remain in a high-impedance state until the processor is granted the bus. after this, the ?rst bus cycle for reset exception processing begins. in figure b-6, the processor assumes implicit ownership of the bus before the ?rst bus cycle begins. the levels on the cdis , js1 (mdis on the mc68040), and ipl2 Cipl0 signals are not sampled when rsti is negated. for processor resets after the initial power-on reset, should be asserted for at least 10 clock periods. figure b-6 illustrates timing associated with a reset when the processor is executing bus cycles. note that bb and tip (and ta driven during a snooped access) are asserted before transitioning to a three-state level. processor reset causes any bus cycle in progress to terminate as if ta or tea had been asserted. also, the processor initializes registers appropriately for a reset exception. when a reset instruction is executed, the processor drives the reset out (rsto ) signal for 512 bclk cycles. in this case, the processor resets the external devices of the system, and the internal registers of the processor are unaffected. the external devices connected to rsto are reset at the completion of the reset instruction. an rsti signal that is asserted to the processor during execution of a reset instruction immediately resets the processor and causes rsto to negate. rtso can be logically anded with the external signal driving
b-8 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) rtsi to derive a system reset signal that is asserted for both an external processor reset and execution of a reset instruction. figure b-5. MC68EC040 initial power-on reset timing figure b-6. MC68EC040 normal reset timing
motorola m68040 users manual b-9 MC68EC040 rev2.2 (11/02/99) b.5 exception processing the MC68EC040 provides ?ve different stack frames for exception processing and allows for a mc68040-speci?c stack frame. refer to section 8 exception processing for details on exception processing. b.5.1 unimplemented floating-point instructions and exceptions all legal mc68040 and mc68881/mc68882 ?oating-point instructions are de?ned as unim- plemented ?oating-point instructions on the MC68EC040. these instructions generate an eight-word stack frame (format $4) during exception processing before taking an f-line exception. these instructions trap as an f-line exception and can be emulated in software by the f-line exception handler to maintain user-object-code compatibility. the MC68EC040 assists the emulation process by distinguishing unimplemented ?oat- ing-point instructions from other unimplemented f-line instructions. to aid emulation, the effective address is calculated and saved in the format $4 stack frame. this simpli?es and speeds up the emulation process by eliminating the need for the emulation routine to deter- mine the effective address and by providing information required to emulate the instruction on the exception stack frame in the supervisor address space. however, the ?oating-point instruction can reside in user space; therefore, the ?oating-point unimplemented exception handler may need to access user instruction space. the following processing steps occur for an unimplemented ?oating-point instruction: 1. when an unimplemented floating-point instruction is encountered, the instruction is partially decoded, and the effective address is calculated, if required. 2. the processor waits for all previous integer instructions, write-backs, and associated exception processing to complete before beginning exception processing for the un- implemented floating-point instruction. any access error that occurs in completing the write-backs causes an access error exception, and the resulting stack frame indicates a pending unimplemented floating-point instruction exception. the access error ex- ception handler then completes the write-backs in software, and exception processing for the unimplemented floating-point instruction exception begins immediately after re- turn from the access error handler. 3. the processor begins exception processing for the unimplemented floating-point in- struction by making an internal copy of the current sr. the processor then enters the supervisor mode and clears the trace bits (t1 and t0). it creates a format $4 stack frame and saves the internal copy of the sr, pc, vector offset, calculated effective ad- dress, and pc value of the faulted instruction in the stack frame. the effective address field of the format $4 stack frame contains the calculated effec- tive address of the operand for the faulted floating-point instruction using the address- ing mode in which the effective address is calculated. for immediate and register direct addressing modes, this field is $0. the saved pc value is the logical address of the instruction that follows the unimplemented floating-point instruction. this value will be restored during rte execution. the vector offset format number ($4) is used for this eight-word stack frame. note that an mc68040 cannot correctly handle a stack for- mat $4. the pc of the faulted instruction contains a long-word pc of the floating-point instruction that caused the trap to occur. the information is provided so that the in-
b-10 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) struction is available for software emulation of floating-point instructions. the proces- sor generates exception vector number 11 for the unimplemented f-line instruction exception vector, fetches the address of the f-line exception handler from the excep- tion vector table, and begins execution of the handler after prefetching instructions to fill the pipeline. refer to section 8 exception processing for details about exception processing. b.5.2 MC68EC040 stack frames when the processor executes an rte instruction, it examines the stack frame on top of the active supervisor stack to determine if it is a valid frame and what type of context restoration it requires. the set of stack frames included for exception processing are four- and six-word stack frames, a four-word throwaway stack frame, an access error stack frame, and a new eight-word unimplemented ?oating-point stack frame. the stack frame that the mc68040 can generate and the MC68EC040 can process is the ?oating-point post-instruction stack frame. refer to section 8 exception processing for details about exception stack frames. when the MC68EC040 writes or reads a stack frame, it uses long-word operand transfers wherever possible. using a long-word-aligned stack pointer greatly enhances exception pro- cessing performance. the processor does not necessarily read or write the stack frame data in sequential order. the system software should not depend on a particular exception gen- erating a particular stack frame. for compatibility with future devices, the software should be able to handle any type of stack frame for any type of exception. the MC68EC040 does not generate the ?oating-point post-instruction stack frame. the mc68040 cannot accept the eight-word unimplemented stack frame. the MC68EC040 can handle all mc68040 stack frame formats. b.6 software considerations the following MC68EC040 instructions are different from the mc68040: ptest, pflush, cpush, cinv, movec, and all ?oating-point instructions. the ptest and pflush instructions should not be executed. execution of the ptest instruction causes random bus cycles to occur. execution of the pflush instruction produces indeterminate results. neither instruction causes the MC68EC040 to generate an exception. the cpush and cinv instructions require special consideration. a page is de?ned as a 4-kbyte block of external memory. the cpush and cinv page instruction opcodes can be used to push or invalidate 4-kbyte blocks of memory. the MC68EC040 does not support 8-kbyte pages. the movec to urp and srp instructions are not valid and will produce indeterminate results. each acu has a status register and translation control register that replace the mmu eight-word stack frame (format $4) stack frames exception types stacked pc points to (unable to locate art) the mc68040 cannot generate or read this stack. effective address field is the address of the faulted instruction operand.
motorola m68040 users manual b-11 MC68EC040 rev2.2 (11/02/99) status register and translation control register of the mc68040. the mmu status register opcode of the movec instruction can modify the acu status register. the MC68EC040 acu status register does not provide additional functionality to the acu and is only provided for compatibility with the acu mc68ec030 status register. the acu status register may not be implemented in future m68ec0x0 products. b.7 MC68EC040 electrical characteristics the following paragraphs provide information on the maximum rating and thermal charac- teristics for the MC68EC040 only. refer to appendix c mc68040v and MC68EC040v for more information on electrical characteristics for the MC68EC040v. this section is subject to change. for the most recent speci?cations, contact a motorola sales of?ce or complete the registration card at the end of this manual. b.7.1 maximum ratings b.7.2 thermal characteristics table 12-2. characteristic symbol value unit this device contains protective circuitry against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliablity of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). supply voltage v cc C0.3 to +7.0 v input voltage v in C0.5 to +7.0 v maximum operating junction temperature t j 110 c minimum operating ambient temperature t a 0 c storage temperature range t stg C55 to 150 c characteristic symbol value rating thermal resistance, junction to case pga package q jc 3 c/w
b-12 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) b.7.3 dc electrical specifications (v cc = 5.0 vdc 5 %) *capacitance is periodically sampled rather than 100% tested. b.7.4 power dissipation *this information is for system reliability purposes. characteristic symbol min max unit input high voltage v ih 2 v cc v input low voltage v il gnd 0.8 v undershoot 0.8 v input leakage current @ 0.5C2.4 v avec , bclk, bg , cdis , ipl? , pclk, rsti , scx, tbi , tlnx, tci , tck, tea i in 20 20 ma hi-z (off-state) leakage current @ 0.5C2.4 v an, bb , ciout , dn, lock , locke , r/w , sizx, ta , tdo, tip , tmx, tlnx, ts , ttx, upax i tsi 20 20 ma signal low input current, v il = 0.8 v tms, tdi, trst i il C1.1 C0.18 ma signal high input current, v ih = 2.0 v tms, tdi, trst i ih C0.94 C0.16 ma output high voltage, i oh = 5 ma v oh 2.4 v output low voltage, i ol = 5 ma v ol 0.5 v capacitance*, v in = 0 v, f = 1 mhz c in 25pf frequency watts maximum values (v cc = 5.25 v, t a = 0 c) 20 mhz 3.2 25 mhz 3.9 33 mhz 4.9 40 mhz tbd typical values (v cc = 5 v, t a = 25 c)* 20 mhz 2.0 25 mhz 2.4 33 mhz 3.0 40 mhz tbd
motorola m68040 users manual b-13 MC68EC040 rev2.2 (11/02/99) b.7.5 clock ac timing specifications (see figure b-7) *speci?cation value at maximum frequency of operation. 20 mhz 25 mhz 33 mhz 40 mhz unit num characteristic min max min max min max min max frequency of operation 16.67 20 16.67 25 16.67 33.3 20 40 mhz 1 pclk cycle time 25 30 20 30 15 30 12.5 25 ns 2 pclk rise time 1.7 1.7 1.7 1.5 ns 3 pclk fall time 1.6 1.6 1.6 1.5 ns 4 pclk duty cycle measured at 1.5 v 48 52 47.5 52.5 46.67 53.33 46.00 54.00 % 4a* pclk pulse width high measured at 1.5 v 12 13 9.5 10.5 7 8 5.75 6.75 ns 4b* pclk pulse width low measured at 1.5 v 12 13 9.5 10.5 7 8 5.75 6.75 ns 5 bclk cycle time 50 60 40 60 30 60 25 50 ns 6,7 bclk rise and fall time 4433ns 8 bclk duty cycle measured at 1.5 v 40 60 40 60 40 60 40 60 % 8a* bclk pulse width high measured at 1.5 v 20 30 16 24 12 18 10 15 ns 8b* bclk pulse width low measured at 1.5 v 20 30 16 24 12 18 10 15 ns 9 pclk, bclk frequency stability 1000 1000 1000 1000 ppm 10 pclk to bclk skew 99n/an/ans figure b-7. clock input timing diagram
b-14 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) b.7.6 output ac timing specifications (see figures b-8 * to b-12) *output timing is speci?ed for a valid signal measured at the pin. timing is speci?ed driving an unterminated 30- w transmission line with a length characterized by a 2.5-ns one-way propagation delay. buffer output impedance is typically 30 w ; the buffer speci?cations include approximately 5 ns for the signal to propagate the length of the transmission line and back. 20 mhz 25 mhz 33 mhz 40 mhz unit num characteristic min max min max min max min max 11 bclk to address ciout , lock , locke , r/w , sizx, tlnx,tmx, ttx, upax valid 11.5 35 9 30 6.5 25 5.25 24 ns 12 bclk to output invalid (output hold) 11.5 9 6.5 5.25 ns 13 bclk to ts valid 11.5 35 9 30 6.5 25 5.25 24 ns 14 bclk to tip valid 11.5 35 9 30 6.5 25 5.25 24 ns 18 bclk to data-out valid 11.5 37 9 32 6.5 27 5.25 26 ns 19 bclk to data-out invalid (output hold) 11.5 9 6.5 5.25 ns 20 bclk to output low impedance 11.5 9 6.5 5.25 ns 21 bclk to data-out high imped- ance 11.5 25 9 20 6.5 17 5.25 16 ns 38 bclk to address, ciout , lock , locke , r/w , sizx, ts , tlnx, tmx, ttx, upax high impedance 11.5 23 9 18 6.5 15 13 32 ns 39 bclk to bb , ta , tip high imped- ance 23 33 19 28 14 25 13 ns 40 bclk to br , bb valid 11.5 35 9 30 6.5 23 5.25 14 ns 43 bclk to mi valid 11.5 35 9 30 6.5 25 13 19 ns 48 bclk to ta valid 11.5 35 9 30 6.5 25 13 34 ns 50 bclk to ipend , pstx, rsto valid 11.5 35 9 30 6.5 25 5.25 14 ns
motorola m68040 users manual b-15 MC68EC040 rev2.2 (11/02/99) b.7.7 input ac timing specifications (see figures b-8 to b-12) 20 mhz 25 mhz 33 mhz 40 mhz unit num characteristic min max min max min max min max 15 data-in valid to bclk (setup) 6543ns 16 bclk to data-in invalid (hold) 5443ns 17 bclk to data-in high impedance (read followed by write) 61 49 36.5 30.25 ns 22a ta valid to bclk (setup) 12.5 10 10 8 ns 22b tea valid to bclk (setup) 12.5 10 10 9 ns 22c tci valid to bclk (setup) 12.5 10 10 9 ns 22d tbi valid to bclk (setup) 14 11 10 9 ns 23 bclk to ta , tea , tci , tbi in- valid (hold) 2.5222ns 24 avec valid to bclk (setup) 6555ns 25 bclk to avec invalid (hold) 2.5 222ns 41a bb valid to bclk (setup) 8778ns 41b bg valid to bclk (setup) 10 872ns 41c cdis valid to bclk (setup) 12.5 10 88ns 41d ipl? valid to bclk (setup) 5433ns 42 bclk to bb , bg , cdis , ipl? in- valid (hold) 2.52212ns 44a address valid to bclk (setup) 10 875ns 44b sizx valid to bclk (setup) 15 12 84ns 44c ttx valid to bclk (setup) 7.5 6 8.5 7 ns 44d r/w valid to bclk (setup) 7.7 657ns 44e scx valid to bclk (setup) 12.5 10 11 8 ns 45 bclk to address sizx, ttx, r/w , scx invalid (hold) 2.5223ns 46 ts valid to bclk (setup) 6592ns 47 bclk to ts invalid (hold) 2.5 227ns 49 bclk to bb high impedance (MC68EC040 assumes bus mastership) 1199 8ns 51 rsti valid to bclk 6548.5ns 52 bclk to rsti invalid 2.5 225ns
b-16 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) figure b-8. read/write timing
motorola m68040 users manual b-17 MC68EC040 rev2.2 (11/02/99) figure b-9. bus arbitration timing figure b-10. snoop hit timing
b-18 m68040 users manual motorola MC68EC040 rev2.2 (11/02/99) figure b-11. snoop miss timing figure b-12. other signal timing

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